The fabrication of semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor device using a large number of semiconductor fabrication and metrology processes to form various features and multiple layers of the semiconductor devices. Some fabrication processes utilize photomasks/reticles to print features on a semiconductor device such as a wafer. As semiconductor devices become smaller and smaller laterally and extended vertically, it becomes critical to develop enhanced inspection and review devices and procedures to increase sensitivity and throughput of wafer and photomask/reticle inspection processes.
Semiconductor devices may develop defects during the fabrication processes. Inspection processes are performed at various steps during a semiconductor manufacturing process to detect defects on a specimen. Inspection processes are an important part of fabricating semiconductor devices such as integrated circuits. These inspection processes become even more important to successfully manufacture acceptable semiconductor devices as the dimensions of semiconductor devices decrease. Detection of defects has become highly desirable as the dimensions of semiconductor devices decrease, as even relatively small defects may cause unwanted aberrations in the semiconductor devices. Detecting defects may require accurate alignment of reference images and test images of a semiconductor device via an image alignment process. The image alignment process may include measuring the offset between the reference images and the test images and shifting the reference images and/or the test images by the measured offsets.
Image alignment processes known in the art include coarse alignment processes, which achieve accuracy to within ±one pixel everywhere on the semiconductor device. Coarse alignment processes that align images for an entirety of a swath or select zones of a swath use fewer alignment targets that may be qualified for measuring alignment offsets. If the alignment target is not present and/or the offset measurement is incorrect, alignment accuracy can be poor, and any subsequent defect detection may include false defects caused by misalignment between the coarsely-aligned test and reference images.
Other image alignment processes known in the art include hardware runtime alignment (RTA) processes which can perform alignment across dies from the same scan. Hardware RTA processes may have issues with sparse patterns and large areas of repeating patterns. In addition, the alignment processes may only be able to align die to die within the same scan. Further, hardware RTA processes can only align images with small initial offset and are not flexible to handle large image offset, such as 20 pixels, due to hardware limitations.
Therefore, it would be desirable to provide a method and system for the alignment of semiconductor device reference images and test images, that cures the shortcomings as described above.